Cache type: 5V SRAM, 15 or 20ns, see table below.





DRAM type: 5V FP or EDO mode, with or without parity


           Support 256K, 512K, 1M, 2M, 4M, 16Mx32 SIMM module


           60 or 70ns, see table below.











CMOS Chipset Option     CPU bus Clock 


                        25         33         40         50MHz


-70ns EDO DRAM Non-Cache timing 


DRAM Read Timin         Fastest    Faster     Faster     Faster	


DRAM Write Timing       Fastest    Fastest    Faster     Faster





-60nS EDO DRAM Non-cache timing


DRAM Read Timing        Fastest    Fastest    Faster     Faster	


DRAM Write Timing       Fastest    Fastest    Faster     Faster





-60nS/70nS FP/EDO DRAM Cached timing


DRAM Read Timing        Nornal     Normal     Normal     Normal	


DRAM Write Timing       Normal     Normal     Normal     Normal





L2 cache timing


SRAM Read Timing        2-1-1-1    2-1-1-1(*) 4-2-2-2    4-2-2-2


SRAM Write Timing       0W         0W         0W         0W








* For Intel, AMD, Cyrix and Ti CPU


    - Both Tag and Data SRAM = -15nS


    - If Tag and Data SRAM = -20nS, please change to 4-2-2-2


    - If Tag SRAM = -15nS and Data SRAM = -20nS, PLease change to 3-2-2-2.


  For UMC CPU


    - Both Tag and Data SRAM = -15ns, please change to 3-1-1-1


    - If Tag SRAM = -15ns or -20ns, and Data SRAM = -20ns, please change to 4-2-2-2.


   





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